Keynote Speakers

Title: Stable and Efficient Recurrent Neural Networks

Despite having remarkable performance on many sequence learning tasks, recurrent neural networks (RNNs) are hard to train with long sequences due to limited expressive power and the vanishing and exploding gradient issues. Previous work has focused on stabilizing the gradients by encouraging orthogonality of weight matrices via re-parameterization techniques. However, two major issues remain in these methods. First, the re-parameterization often relies on a chain of operations on small matrices or vectors that are not friendly to hardware accelerators. As a result, it becomes a source of performance bottleneck for training. Second, these methods fix the singular values of the transition matrix throughout the temporal dimension, which further restricts the expressive power of the model and wastes the potential of encoding useful information into the singular values. In this talk, I will present the Singular Value Gated RNN that can efficiently encode temporal information into singular values, as well as mitigate the vanishing and exploding gradient problems. In addition, we can design novel forward and backward propagation algorithms that are friendly to hardware accelerators. This leads to 3-4 times speedup on GPUs and greatly reduces memory cost. On contemporary applications like voice recognition and text summarization, where long term dependencies are hard to capture, the proposed method outperforms other recurrent models with similar or smaller model sizes. This is a joint work with Jiong Zhang of UT Austin.

Inderjit Dhillon is the Gottesman Family Centennial Professor of Computer Science and Mathematics at UT Austin, where he is also the Director of the ICES Center for Big Data Analytics. Currently he is on leave from UT Austin and works as Amazon Fellow at A9/Amazon, where he is developing and deploying state-of-the-art machine learning methods for Amazon search. His main research interests are in big data, machine learning, network analysis, linear algebra and optimization. He received his B.Tech. degree from IIT Bombay, and Ph.D. from UC Berkeley. Inderjit has received several awards, including the ICES Distinguished Research Award, the SIAM Outstanding Paper Prize, the Moncrief Grand Challenge Award, the SIAM Linear Algebra Prize, the University Research Excellence Award, and the NSF Career Award. He has published over 175 journal and conference papers, and has served on the Editorial Board of the Journal of Machine Learning Research, the IEEE Transactions of Pattern Analysis and Machine Intelligence, Foundations and Trends in Machine Learning and the SIAM Journal for Matrix Analysis and Applications. Inderjit is an ACM Fellow, an IEEE Fellow, a SIAM Fellow and an AAAS Fellow.

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Title: Understanding Visual Appearance from Micro Scale to Global Scale

Mixed reality environments require understanding scenes, and then seamlessly blending the rich visual appearance of real and virtual materials to create a compelling user experience. In this talk I will describe our work on modeling and recognizing complex materials, and visual recognition. Using these algorithms as core building blocks we can understand appearance at a global scale by mining social media to discover visual patterns across geography and time. This talk will describe our work on understanding global fashion styles and trends.

Kavita Bala is the Chair of the Computer Science Department at Cornell University. She received her S.M. and Ph.D. from the Massachusetts Institute of Technology (MIT), and her B.Tech. from the Indian Institute of Technology (IIT, Bombay). She was a post doctoral researcher at the Program of Computer Graphics. She co-founded GrokStyle (acquired by Facebook), and is a faculty Fellow with the Atkinson Center for a Sustainable Future. Bala specializes in computer vision and computer graphics, leading research in recognition and visual search using deep learning; material modeling and acquisition using physics and learning; realistic, physically-based rendering; and material and lighting perception. Bala's work on scalable rendering, Lightcuts, is the core production rendering engine in Autodesk's cloud renderer; and her instance recognition research is the core technology of GrokStyle's visual search engine. Her work on 3D Mandalas was featured at the Rubin Museum of Art, New York.

Bala serves on SIGGRAPH's Papers Advisory Group (PAG). Bala has served as the Editor-in-Chief of Transactions on Graphics (TOG), on the Papers Advisory Board for SIGGRAPH and SIGGRAPH Asia, and as Associate Editor for TOG (Transactions on Graphics), TVCG (Transactions on Visualization and Computer Graphics) and CGF (Computer Graphics Forum). Bala has co-authored the graduate-level textbook "Advanced Global Illumination" (A K Peters publisher, second edition). She has chaired SIGGRAPH Asia 2011, and co-chaired Pacific Graphics (2010) and the Eurographics Symposium on Rendering (2005).

Bala has received the NSF CAREER award, Cornell's College of Engineering Fiona Li and Donald Li Excellence in Teaching Award (2015), James and Mary Tien Excellence in Teaching Award (2006 and 2009), and the Affinito-Stewart award.

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Title: Determinism and energy efficiency in Industrial IoT

Industrial applications, such as smart grid, smart manufacturing or automotive industry applications, require ultra low-latency, ultra low-power consumption and high network reliability. The Time Slotted Channel Hopping (TSCH) mode of IEEE802.15.4 can provide these characteristics; however, as all the wireless technologies, it is prone to internal and external interference. A number of techniques to mitigate or avoid potential collisions since the formation of the network is described. Moreover, promising wireless power transfer methods are introduced to provide energy efficiency and even power autonomy to Industrial Internet of Things (IIoT) applications.

Christos Douligeris, currently a professor at the department of Informatics, University of Piraeus, Greece held positions with the Department of Electrical and Computer Engineering at the University of Miami. He was an associate member of the Hellenic Authority for Information and Communication Assurance and Privacy and the President and CEO of Hellenic Electronic Governance for Social Security SA.Dr. Douligeris has published extensively in the networking scientific literature and he has participated in many research and development projects. He is the co-editor of a book on ‘‘Network Security’’ published by IEEE Press/ John Wiley and he is on the editorial boards of several scientific journals as well as on the technical program committees of major international conferences.

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Title: AI and ML in Manufacturing – Past, Present and Future

Artificial Intelligence and Machine Learning have played a significant role since the early 1980s in Manufacturing. From the first NSF ERC on Intelligent Manufacturing to the current DoE’s CESMII, AI has played a significant role. This talk will focus on the application of AI and ML to solve several relevant manufacturing problems and discuss the future impact of this new paradigm. We will discuss the history of AI starting with the Intelligent Manufacturing Systems of the 1980s to look into the future from a personal viewpoint.We will emphasize the need for a new science of ML using IoT data, real-time nonlinear data analysis and community detection in networks. We will discuss the smart manufacturing of the future which will be combining the matching features of Uber, google search mechanisms, and Amazon’s distribution formalisms leading to manufacture anytime, anywhere a reality..

Soundar Kumara is the Allen, E., and Allen, M., Pearce Chaired Professor of Industrial Engineering at Penn State. Has an affiliate appointment with the school of Information Sciences and Technology. He serves as an Adjunct Professor at the C.R. Rao Institute of Advanced Mathematics, Statistics and Computer Science, University of Hyderabad, India. His research interests are in Data Science, AI and Machine Learning in Manufacturing and Healthcare He is a Fellow of Institute of Industrial Engineers (IIE), Fellow of the International Academy of Production Engineering (CIRP), and Fellow of American Association for Advancement of Science (AAAS), and American Association of Mechanical Engineers (ASME).He has won several awards including the Faculty Scholar Medal (highest research award at PSU), PSU Graduate Teaching Award, Penn State Engineering Society Outstanding Advisor Award, Premier Research Award, and PSES Outstanding Research Award. He has more than 200 publications to his credit and several of his papers have won best paper awards. His publication on clustering large networks in Physics Reviews – E ( 2007) is chosen by the PRE editorial board as the milestone paper for 2007 (about 25 papers were picked by PRE in 2018 over 25 years of 5000 published papers). Dr. Kumara held visiting professorships at some of the leading institutions in the world including; Massachusetts Institute of Technology, University of Tokyo, City University of Hong Kong and Korea Institute of Science and Technology. 55 Ph.D., and 66 MS students graduated under his guidance. Dr. Kumara got his Bachelor of Engineering degree from S.V.U. College of Engineering, Tirupati; Master of Technology degree from IIT Madras, India; and Ph.D., from Purdue University. His Erdős number is 3.His google citations is around 9300, with a h-index of 41 and i10 index of 121. A couple of links:

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Title: A Multi-sensor System for Traffic Analysis at Smart Intersections

We present a multi-sensor system for vehicle and pedestrian traffic analysis and visualization at intersections to discover trajectory patterns and anomalous traffic behavior. Augmenting these data with signal and phasing information, we show how clustering in the context of signal information may help us to detect anomalies with respect to vehicles violating signals. We demonstrate our workflow on two intersections with very different traffic composition. The system may be leveraged by a number of other applications, including conflict detection in object movements, turn movement counts, incident detection and management, and demand profiling, for better traffic management through the adjustment of signal timing.

Sanjay Ranka is a Professor in the Department of Computer Information Science and Engineering at University of Florida. His current research interests are high performance and parallel computing with a focus on energy efficiency; and big data science with a focus on data mining/machine learning algorithms for spatiotemporal applications. His work is driven by applications in CFD, remote sensing, health care and transportation. He teaches courses on data science (three course curriculum), data mining and parallel computing.

From 1999-2002, he was the Chief Technology Officer at Paramark (Sunnyvale, CA). At Paramark, he developed a real-time optimization service called PILOT for marketing campaigns. PILOT served more than 10 million optimized decisions a day in 2002 with a 99.99% uptime. Paramark was recognized by VentureWire/Technologic Partners as a top 100 Internet technology company in 2001 and 2002 and was acquired in 2002. He has also held positions as a tenured faculty positions at Syracuse University and as a researcher/visitor at IBM T.J. Watson Research Labs and Hitachi America Limited.

Sanjay earned his Ph.D. (Computer Science) from the University of Minnesota and a B. Tech. in Computer Science from IIT, Kanpur, India. He has coauthored four books, 250+ journal and refereed conference articles. His recent co-authored work has received a best student paper runner up award at IGARSS 2015, best paper award at BICOB 2014, best student paper award at ACM-BCB 2010, best paper runner up award at KDD-2009, a nomination for the Robbins Prize for the best paper in journal of Physics in Medicine and Biology for 2008, and a best paper award at ICN 2007.

He is a fellow of the IEEE and AAAS, and a past member of IFIP Committee on System Modeling and Optimization. He is an associate Editor-in-Chief of the Journal of Parallel and Distributed Computing and an associate editor for ACM Computing Surveys, IEEE/ACM Transactions on Computational Biology and Bioinformatics, Sustainable Computing: Systems and Informatics, Knowledge and Information Systems, and International Journal of Computing. He is also an edittorial board member of Applied Sciences (Compuing and Artificial Intelligence). Additionally, he is a book series editor for CRC Press for Bigdata. In the past, he has been an associate editor for IEEE Transactions on Parallel and Distributed Systems and IEEE Transactions on Computers.

He was a past member of the IFIP Committee on System Modeling and Optimization, Parallel Compiler Runtime Consortium, the Message Passing Initiative Standards Committee and Technical Committee on Parallel Processing. He is the program chair for 2015 High Performance Computing, 2013 International Parallel and Distributed Processing Symposium, 2010 International Conference on Contemporary Computing and co-general chair for 2009 International Conference on Data Mining and 2010 International Conference on Green Computing.

Sanjay has had consulting assignments with a number of companies (AT∧T Wireless, IBM, Hitachi) and has served as an expert witness in patent disputes. He is a series editor for CRC press on Bigdata. His work has received 10000+ citations with an h-index of 49 (based on Google Scholar).

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Title: Two Tales of Cache Optimization: Technology-oblivious and Technology-aware

An important class of processor cache optimization techniques attempts to improve the cache hit rate. These techniques are based on reuse-based principles that abstract away the technology used to build the cache. In the first part of the talk, I will follow this traditional cache design principle and present a technique that dynamically learns reuse probability at run-time and employs the learned probabilities to design high-performance cache management policies. We have applied this generic technique to a number of different scenarios employing SRAM caches such as shared last-level cache of multi-core CPUs, last-level cache of discrete GPUs, and shared last-level cache of CPU-GPU heterogeneous multiprocessor SoCs.

In the second part of the talk, I will attempt to apply similar reuse-driven techniques to optimize DRAM caches and show that such a principle is met with the counter-intuitive trend where performance may degrade with increasing hit rate. I will present a simple theory that takes into account the DRAM technology constraints to understand this phenomenon. I will use this theory to design DRAM caches that perform close to the optimal operating point.

Biography: Mainak Chaudhuri is the Poonam and Prabhu Goel Chair Professor of computer science and engineering at Indian Institute of Technology Kanpur. He completed his undergraduate education from Indian Institute of Technology Kharagpur and obtained his MS and PhD degrees from Cornell University. He has been a member of the faculty of computer science and engineering at Indian Institute of Technology Kanpur since 2004. His research area is computer architecture and he teaches undergraduate and graduate courses in computer systems. His research collaboration with the Intel Achitecture Group and the Intel Microarchitecture Research Lab has significantly influenced the cache hierarchy architecture of Intel's client and server processors. He was a recipient of Intel's Technology Excellence award in the year 2018. His research has also won two best paper awards at the International Symposium on High Performance Computer Architecture (HPCA), a top-tier venue for publishing computer architecture research results. Mainak has been a recipient of the IBM Faculty award and Microsoft Research India young faculty award. Mainak has served on the program committee of several top-tier computer architecture conferences and was an associate editor of IEEE Computer Architecture Letters and ACM Computing Surveys. Since 2016 he has been a member of the eight-member R & D expert group in the Indian National Supercomputing Mission (NSM).

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Title: Model-Based Safety Analysis in Cyber-Physical Systems

Abstract: Cyber-Physical Systems abound us. They combine Cyber---Software for networking and decision-making, and Physical components. Accordingly, their behaviors comprise of hybrid of discrete and continuous states, and are modeled as hybrid automata. Simulink/Stateflow is a commonly used modeling and simulation platform for cyber-physical systems consisting of reactive embedded code that interacts with its environment in real-time fashion. This talk will present an approach for safety analysis of Simulink/Stateflow models, based on its automated translation to input-output extended finite automaton (I/O-EFA), followed by automated test-generation, guaranteeing user-defined code as well as requirements coverage, and also support for automated test-execution and error-localization. While testing is useful for design-time error analysis, the talk will further discuss our model-based approach for run-time error monitoring, detection and localization. Monitoring at CPS level (as opposed to software level) is necessarily stochastic, and a more general I/O-Stochastic Hybrid Automaton (I/O-SHA) model is used, and condition for bounded-delay detectability, and achieving desired levels of false-positives/-negatives will be discussed. The talk also presents our simulation-based approach for safely analysis of hybrid systems, where a finite number of simulation runs are used to confirm bounded-horizon safety, useful for run-time assurance.

Biographical Sketch: Ratnesh Kumar (F’07) is a Harpole Professor at the Iowa State University, Electrical and Computer Engineering, where he directs the ESSeNCE (Embedded Software, Sensors, Networks, Cyberphysical, an Energy) Lab. Previously, he held faulty position at the University of Kentucky, and various visiting positions with the University of Maryland, the Applied Research Laboratory at the Pennsylvania State University, the NASA Ames, the Idaho National Laboratory, the United Technologies Research Center, and the Air Force Research Laboratory. He received a B. Tech. degree in electrical engineering from IIT Kanpur, India, and the M.S. and Ph.D. degrees in electrical and computer engineering from The University of Texas at Austin. Ratnesh was a recipient of the Gold Medals for the Best EE Undergrad, the Best EE Project, and the Best All Rounder from IIT Kanpur, the Best Dissertation Award from UT Austin, the Best Paper Award from the IEEE Transactions on Automation Science and Engineering, and Keynote Speaker and paper awards recipient from multiple conferences. He is or has been an editor of several journals (including of IEEE, SIAM, ACM, Springer, IET, MDPI), is a Distinguished Lecturer of the IEEE Control Systems Society, recipient of D. R. Boylan Eminent Faculty Award for Research from Iowa State University, a Fellow of IEEE, and also a Fellow of AAAS.

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